A1 Deep dive
Unauthenticated Inference Endpoint
Public inference route accepts requests without an identity boundary at the Raspberry Pi gateway.
Pi gateway / public API / CIA
A2 Deep dive
Resource Exhaustion / DoS
Request bursts, oversized payloads, or slow clients saturate the gateway queue and accelerator path.
Ingress queue / rate limit / availability
A3 Deep dive
Broken Object Authorization
Prediction records, jobs, or model artifacts are accessed by ID without tenant ownership checks.
API object IDs / result store / STRIDE
A4 Deep dive
Model Update Tampering
Unsigned or weakly verified model transfers allow a poisoned artifact to reach Jetson or FPGA flows.
GPU factory / artifact signing / integrity
A5 Deep dive
Direct Backend Exposure
Jetson or Zynq backend services become reachable from paths that should only reach the Pi gateway.
LAN2 / firewall / backend isolation
A6 Deep dive
Model Extraction by Querying
Repeated black-box queries approximate decision boundaries or recover sensitive model behavior.
Query telemetry / anomaly detection / D5
A7 Deep dive
Adversarial Input Perturbation
Small input changes manipulate model output while preserving plausible human-level appearance.
Client input / validation / robustness
A8 Deep dive
Unsafe / Sensitive Logging
Prompts, frames, tokens, or labels leak into logs that are easier to copy than the protected service.
Jetson logs / privacy / evidence trails
A9 Inspector
Weak TLS / Plaintext Traffic
Internal traffic between gateway, switch, Jetson, and Zynq exposes payloads or credentials.
LAN links / TLS / confidentiality
A10 Inspector
SSH / Admin Surface Exposure
Management interfaces drift into reachable network zones with weak policy or stale credentials.
Admin plane / hardening / least privilege
A11 Inspector
Supply Chain / Container CVE
Runtime images, Python wheels, or build dependencies introduce vulnerable code into the lab stack.
Build chain / SBOM / patch cadence
A12 Inspector
Switch / VLAN Misconfiguration
Routing or VLAN mistakes collapse the public, DMZ, and private backend trust boundaries.
Switch policy / LAN2 / segmentation
A13 Inspector
Power Side-Channel
Power traces from FPGA inference reveal correlations with computation, data, or key-dependent paths.
Zynq board / measurement / leakage
A14 Inspector
EM Side-Channel
Near-field electromagnetic probes expose localized activity from FPGA fabric or board traces.
Physical lab / EM probe / leakage
A15 Inspector
Fault Injection / Glitch
Clock, voltage, or reset disturbance creates incorrect state transitions in the silicon path.
XADC / timing / availability-integrity
A16 Inspector
Bitstream Tampering
FPGA configuration content is modified or replayed without strong provenance checks.
Bitstream build / D9 / integrity
A17 Inspector
PS/PL Trust Boundary Violation
Processor-system software and programmable-logic interfaces disagree about ownership or memory trust.
AXI / DMA / hardware isolation
A18 Inspector
Timing Side-Channel via Dispatch
Latency differences across Jetson and Zynq execution paths leak model, load, or input structure.
Dispatch timing / queue traces / leakage